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RISC-V

4 min readUpdated October 2026
RISC-V
Type
Open standard instruction set architecture (ISA)
Origin
University of California, Berkeley RISC-V project, 2010
Steward
RISC-V International, Lausanne, Switzerland (since 2020)
Licence
Royalty-free open standard — no licence fees
Extensions
RV32/64/128 integer, M, A, F, D, C, B, V (vector)
Notable adopters
SiFive, Esperanto, Tenstorrent, Ventana, Alibaba T-Head, StarFive, Espressif
Related architectures
Arm, x86
RISC-V is a free and open standard instruction set architecture (ISA) for computer processors, meaning it defines how software commands map to processor hardware, without requiring any licence fees from implementers. It originated as a research project at the University of California, Berkeley in 2010 and is now stewarded by RISC-V International, a nonprofit organisation headquartered in Lausanne, Switzerland.[1]

History

RISC-V descends from Berkeley's RISC research programme of the 1980s — the Reduced Instruction Set Computer projects that David Patterson and colleagues developed, including the RISC I, RISC II and later Berkeley RISC V prototypes whose name inspired the modern architecture's designation.[2] The current RISC-V project began in 2010 at UC Berkeley under Krste Asanović, David Patterson, Andrew Waterman and Yunsup Lee, initially funded by the US Defense Advanced Research Projects Agency (DARPA) alongside industry sponsors.[2]

The RISC-V Foundation was established in 2015 to govern the standard, with founding members that included Google, Hewlett Packard Enterprise, IBM, Intel, Nvidia, Qualcomm and Samsung.[2] In 2020 the project restructured as RISC-V International and relocated its headquarters to Switzerland, a move widely interpreted as a hedge against potential US export-control restrictions on the technology.[3] Membership has since grown to several thousand organisations, making RISC-V one of the most broadly supported open hardware standards in the industry.[1]

Key Concepts and Technology

The defining property of RISC-V is that it is an open standard: the specification is published openly and implementers pay no royalties, in contrast to Arm's licensing-plus-royalty model or the cross-licensing arrangements that govern x86.[3] RISC-V is built from a minimal base integer instruction set (RV32I or RV64I) plus optional standard extensions — such as M (integer multiply/divide), A (atomics), F and D (single and double-precision floating point), C (compressed 16-bit instructions), B (bit manipulation) and V (vector operations) — so designers include only the features they need.[1]

This modularity extends to customisation: chip designers may add proprietary instructions for specialised workloads without licensing the whole architecture, and implementations may vary widely in microarchitecture, from tiny microcontrollers to application-class processors and AI accelerators.[3] The open specification also enables independent security review of processor designs, a property of increasing interest to governments and enterprises.[1]

Applications and Impact

RISC-V is now deployed across an expanding range of products. Espressif's ESP32-C3 and ESP32-C6 microcontrollers, among the most popular Wi-Fi and Bluetooth chips in the world, use RISC-V cores. AI chip company Esperanto built its ES-1 accelerator around more than a thousand RISC-V cores, and Tenstorrent's AI processors use RISC-V cores for control. SiFive's P670 and P870 cores target application-class devices, Alibaba's T-Head division has deployed XuanTie RISC-V processors in servers, and StarFive's boards are widely used in education and prototyping.[2][4] Google has also added RISC-V as a supported architecture for the Android Open Source Project, and RISC-V is the subject of active policy debate — analysts including CSIS have examined the architecture's implications for global chip development and export-control strategy.[3]

>See Also

🇲🇾Malaysian Context

🇲🇾 RISC-V has particular resonance for Malaysia, one of the world's top six semiconductor exporters and a hub for assembly, testing and packaging, which is now seeking to move up the value chain into IC design. The Malaysia Semiconductor IC Design Park in Kulim, Kedah, and the National Semiconductor Strategy (2024) both aim to grow domestic chip-design capabilities.[5] Because RISC-V imposes no licence fees, it lowers the entry cost for Malaysian fabless startups and for educational institutions designing their own processors — a barrier that has traditionally favoured incumbents using Arm or x86.[3]

Malaysian universities are responding: Universiti Sains Malaysia, for example, has integrated RISC-V alongside Arm into its semiconductor education programmes, explicitly framed as building a new generation of local chip designers.[6] With the government's investment in the IC design park and continued emphasis on semiconductor talent through MDEC and HRD Corporation training programmes, RISC-V offers Malaysia an accessible standard on which to build indigenous processor expertise.[5][6]

References

  1. ↑RISC-V International. About RISC-V. https://riscv.org/about/
  2. ↑Wikipedia. RISC-V — history, Berkeley origins and adoption. https://en.wikipedia.org/wiki/RISC-V
  3. ↑CSIS. What RISC-V Means for the Future of Chip Development. https://www.csis.org/analysis/what-risc-v-means-future-chip-development
  4. ↑Espressif. ESP32-C3 — RISC-V based microcontroller. https://www.espressif.com/en/products/socs/esp32-c3
  5. ↑Malaysia Semiconductor IC Design Park. https://www.myicpark.com/
  6. ↑Universiti Sains Malaysia. Advancing semiconductor capability — Arm and RISC-V in local semiconductor education. https://www.facebook.com/USMOfficial1969/posts/1643531701146906/
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